Introduction

Phase Locked Loop(PLL)

Definition

Phase: Quantity to be controlled
Locked: locking means stabilize or make phase difference constant
Loop: Negative Feedback

PLL Design Principles

PLL is a negative feedback system where the output signal frequency is locked to the input signal frequency because control theory states that to control a process you will certainly have a finite and constant error so we will use advantage of control theory of outputting constant error by doing this trick
if we want to control frequency of output wave and make it equal to input wave so we cannot do that control operation direct we will try to control phase of the output signal phase $\phi_{out}$ and make it equal to input signal phase $\phi_{in}$ by that we will have constant frequency as explained in equations below (this principle is very huge as it lead us use the same theory but having zero error)

$$\phi_{in}-\phi_{out}=\phi_e=constant=> \space Lock \space Condition$$ $${dphi_{in} \over dt}-{dphi_{out} \over dt}=0$$ $$\omega_{in}=\omega_{out}$$

for example if want to make acceleration of car as the setpoint we need to control its velocity

Control Theory

1. System Modeling

PLL is like above loop but instead of making Vout traces Vin it make phi out traces Phi like in figure below but we merged the summer with transducer by a block named by phase shift detector(this is the right name) not the one in the figure below because we are sensing the difference between phases not the actual phase
while loop filter is the controller and VCO is the target system

2. Mathematical Modeling

Feedback Control system Mathematical Modeling

$${output \over setpoint}={{G(s)G_c(s)} \over 1+{G_c(s)G(s)H(s)}}$$

3. Analog Devices Modeling

Feedback Control Systems Modeling using Analog devices

Opamp with finite Gain A0 and a feedback circuit using Passive components (R,L,C)

$$V_{out}=A_{OL}(V_{in}-V_{fb})=A_{OL}(V_{in}-\beta V_{out})$$ $$A_{CL}={V_{out} \over V_{in} }= {A_{OL} \over {1+\beta A_{OL}}}={A_{OL} \over {1+LG}}=>{1 \over \beta}$$ $$V_{err}=V_{in}-V_{fb}=V_{in}-\beta V_{out} = V_{in}-\beta A_{OL} V_{err}$$ $$V_{err}={V_{in} \over {1+\beta A_{OL}}}={V_{in} \over {1+LG}}=>0$$ $$LG=LoopGain$$

Phase difference

We can express phase as a linear function of time because its derivative is the angular frequency of sine wave which is usually constant so that we can express the change of phase between two signals by $\Delta \phi$, in the following way: $x_1(t)=V_1sin(wt+\lambda_1)=V_1sin(\phi_1(t))$ and $x_2(t)=V_2sin(wt+\lambda_2)=V_2sin(\phi_2(t))$ $$\omega={d\phi_1 \over dt}={d\phi_2 \over dt}=constant$$ $$\phi_1(t)=wt+\lambda_1, \phi_2(t)=wt+\lambda_2 $$ then we can plot them as two lines as in figure below

working on it — two different initial shifts

if we make $\lambda_1 = \lambda_2=\lambda$ but with two different angular frequencies $\omega_1 , \omega_2$ then we will have two lines with two different slopes but with same interception on y-axis we made $\lambda=0$ in figure below

where also we can express frequency shift keying modulation like in figure below we have two slopes one for $+ve\Delta f$ and one for $-ve\Delta f$

Change in phase Frequency Shift Keying Modulation

Excess Phase & Jitter

PLL Building Blocks

Voltage Controlled Oscillator (VCO):the process which we are trying to control(Voltage-->Frequency)
Phase Shift Detector: transforms phase error signal to AC voltage error signal(Sensor)
Loop Filter:changes AC Voltage signal to a DC Voltage signal for control
Frequency Divider(Digital Block(Modulus-counter or divider)):equal to one

Voltage Controlled Oscillator(Actuator)

We control output frequency using a gain of $K$ and $V_{control}$ where it controls output frequency by the change in input voltage

$$\omega_{out}=\omega_o + K_{VCO}.V_{control}$$ $$\omega_o \space is \space the \space free \space running \space frequency$$ $$K_{VCO} \space is \space the \space gain \space of \space VCO [(rad/sec.)/V][Frequency/Voltage]$$

Phase shift Detector Implementation(Sensor+summer)

we merged sensor with the summer by sensing the difference between phase of output and input signal not the actual phase of both of them and then subtract them

Digital Signals Phase Shift Detector

we implemented phase detector using xor gate but its disadvantage works only for digital signal and second thing is that we have not to increase phase shift than pi or decrease it than zero because that will make phase difference become less than zero which will convert feedback to positive feedback so we work at phase difference of pi/2 but how pll works if we have error because we are targetting to have a constant phase error which leads to zero frequency error

$$\phi_1,\phi_2 ====>Phase Shift Detector(Differential Sensor)====>\Delta V$$

Analog Signals Phase Shift Detector

Loop Filter(Controller)

Loop filter is a low pass filter which integrates on AC signal to get DC voltage signal for controlling VCO

$$\Delta V_{controlDC}=\int \Delta V_{ControlAC} dt ==VCO==> \Delta Frequency=\int \Delta \phi_{phaseshift} dt$$ $$Current \space in \space Branch \space R =I={{V_{in}-V_{out}}\over {R}}$$ $$V_{out}={Q \over c}={{\int I dt} \over c}=\int{{{V_{in}-V_{out} }\over {RC}}dt}$$

Phase shift detection for different cases

case $V_{controlAC}$ is Analog Sinusoidal Signal

Assume $V_{controlAC}$ is $V_m sin(\omega_mt)$ $$\Delta V_{controlDC}=\int \Delta V_{ControlAC} dt ,then,$$ $$V_{out}(t)=V_ocos(\omega_ot+K_{VCO}\int V_{controlAC}dt)=V_ocos(\omega_ot+K_{VCO}{V_m \over \omega_m}sin(\omega_mt))$$ if we decrease $K_{VCO}$ we will have small ripples but $\phi_e$ will increase so that there is a design trade off between both of them

Frequency Divider

Building a digital counter in the form of sequence of flipflops

Behavior of PLL

In steady state (lock condition)
For small perturbation - Qualitative
Quantitative using Small Signal Model

Steady State (Lock Condition)

PLL reached steady state means that phase difference between input and output became constant $\phi_{error}=\phi_{in}-\phi_{out}=constant$ which leads to $\omega_{in}=\omega_{out}$
phase error must be inversely proportional with loop-gain

$$\Delta \phi_e = \phi_{e1} - \phi_{e2} = {{\Delta \omega}\over{K_{PD}K_{VCO}}} @M=1$$

Step Response of input phase on PLL

Block Diagram

Step input

$$V_{in}{(t)}=V_A cos \omega_1 t$$ $$V_{out}{(t)}=V_B cos{(\omega_1 t +\phi_o)}$$

Output(Phase control)

width of VPD determines how much is phase difference which also indicates how much we decrease/increase VCO in order to control Vout lpf acts as integrator so when VPD width increases its value increases which increases VCO precedingly and vice versa

Applications

Frequency synthesizer in a wireless reciever
Clock & Data Recovery in wireline communication
Frequency modulation & demodulation
Skew Cancellation

PLL as Frequency Synthesizer in wireless receiver

after antenna we have a bandpass filter to select a whole band not a channel like in case of a GSM like 800Mhz, 900Mhz, 1800Mhz, 1900Mhz and there are channels inside each band where each channel inside band is of width 200KHz, incase of GSM900 Standard, bandwidth of 5G is 1GHz because of large datarate incase of selecting channels(200KHz) then $Q={900MHz \over 200KHz}=4500$ which is very and not possible thats why we don't select channel at once we select band of channels(25MHz) like $Q={900MHz \over 25MHz}=36$ which is attainable in fact making a very sharp filter like of Q=4500 is achievable using passive filter but the bad thing about it that it will not be programmable thats why we said it is not possible

We have an low noise amplifier to increase signal to noise ratio in order to reject noise then we use the mixer to demodulate the channel to a lower frequency, local oscillator as it will be changed locally inside the receiver to make it centered at baseband then we use a lowpass filter at base band to select the required channel then we use a variable gain amplifier after the Low pass filter but it isnot drawn in the figure because if the input signal is amplified with a constant factor it will saturate adc after the dotted block is a digital processing like what we studied in DSP course, while inside dotted block is analog processing. Our main interest now is in PLL which is used to generate local oscillator (coherence receiver\Voltage controlled oscillator)

Analog Integrated Systems